1. Field of the Invention
The present invention relates in general to analyzing microprocessor based computer systems, and more particularly to real-time data tracing with logic circuitry on the same integrated circuit chip as the microprocessor.
2. Description of Related Art
Embedded microprocessors do not provide to external instrumentation the same accessibility to their I/O signals as found on stand-alone microprocessor modules. This has caused a shift in In-Circuit Emulation (ICE) techniques, originally from using external instrumentation that plugs into a microprocessor socket in place of the microprocessor, to adding various forms of ICE logic on the chip itself. Normally, the on-chip logic has access to the necessary control, address, and data signals required to monitor the embedded microprocessor""s activity and an output port for transferring this information from the chip to other monitoring equipment.
ICE is primarily used for the purpose of developing and debugging the program code before it is released from the factory to the user or consumer. Minimally, ICE requires components that identify a trigger event from which program code is subsequently traced, a means to buffer the trace data, and a means of displaying the trace results on external instrumentation. A programmer is more often concerned with seeing an instruction trace which provides insight to the program flow. Most of the existing prior art solutions address this requirement. However, the need for data tracing at real-time processing speeds using circuitry on the same chip as the embedded microprocessor has not been evident in the art. This solution provides the programmer with information on the data values that have been stored in or read from memory elements by the microprocessor as well as the addresses of those memory elements in real-time.
The problem of accessing data values and their associated memory locations arises with modern processors which can load and store data at high speeds with respect to the bandwidth of the off-chip path. These processors are capable of single cycle load and store instructions at high clock rates resulting in the need to capture bursts of load or store information very rapidly, and to send data, address, and associated load/store indicators off the microprocessor chip to external instrumentation at a fast enough rate to accommodate post-processing and display of the reconstructed trace information. The present invention addresses this deficiency in the art.
Methods described in the prior art typically require more silicon area or a larger footprint in the form of buffer memory, and more I/O pins in order to meet the off-chip bandwidth requirements. Furthermore, these circuits are often removed at the final release of the design and before volume shipments. For example, in U.S. Pat. No. 4,674,089 (the xe2x80x9c""089 patentxe2x80x9d) issued on Jun. 16, 1987 to Poret, et al., entitled xe2x80x9cIN-CIRCUIT EMULATOR,xe2x80x9d a complete In-Circuit Emulation circuit originally designed for use with an Intel 16 bit CISC processor is taught. The circuit is intended to be on the same chip as the microprocessor, but is removed prior to production. The ""089 patent ICE circuit determines if captured data should be stored into a memory based on the results of a comparison test. It teaches and discloses a method using a content addressable memory and software programmable logic in the form of a programmable logic array (PLA). In contrast, the present invention""s circuitry is not removed prior to production or shipping, and uses multiple event filters based on range comparison logic to perform the stored memory determination.
Similarly, U.S. Pat. No. 5,491,793, (the xe2x80x9c""793 patentxe2x80x9d) issued on Feb. 13, 1996, to Somasundaram, et al., entitled xe2x80x9cDEBUG SUPPORT IN A PROCESSOR CHIP,xe2x80x9d teaches an ICE circuit used to support code debugging for a 32 bit RISC processor on a single chip. However, unlike the present invention, the ""793 patent design applies to instruction tracing only, and its central processing unit must rely on external instrumentation to set trigger points or break points.
The prior art has not addressed previously the ability to work without instruction tracing. In the present invention, the designer is allowed to implement only the trace unit, or both the instruction and data trace units. Additionally, the information required by trace reconstruction software to combine separate instruction and data tracing data streams is available in the present invention, but absent in the prior art.
I/O pin count represents another existing area of concern in the prior art. The present invention allows for a trade-off of the number of I/O pins used for the data path against the probability of losing events. Similarly, the architecture of the present invention allows the designer to trade-off the FIFO (First-In First-Out) register size with the probability of losing events; an advantage not currently realized in the prior art.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an integrated real-time data tracing apparatus on the same chip as the microprocessor, designed not to be removed prior to production or shipping.
It is another object of the present invention to provide on-chip logic having access to control, address, and data signal lines required to monitor an embedded microprocessor""s activities.
A further object of the invention is to provide an integrated real-time data tracing apparatus on the same chip as the microprocessor requiring less I/O pins to meet the off-chip bandwidth requirements.
It is yet another object of the present invention to provide an integrated real-time data tracing apparatus that works with or without instruction tracing.
A further object of the invention is to provide an integrated real-time data tracing apparatus that allows for synchronization with the instruction trace stream.
Another object of the invention is to provide an integrated real-time data tracing apparatus that allows for a trade-off of the number of I/O pins used for the data path against the probability of losing events.
Yet another object of the invention is to provide an integrated real-time data tracing apparatus that allows for the selection of multiple ranges for tracing.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, an integrated real-time data tracing apparatus for analyzing microprocessor based computer systems, comprising: an embedded core controller; a processor local bus connected to the core controller; a memory controller interfacing to the processor local bus; an embedded random access memory accessible by the memory controller; an instruction cache and a data cache interfacing with the core controller; an instruction side on-chip memory and a data side on-chip memory interfacing with the core controller; and, a data trace unit connected to the data-side on-chip memory and to an auxiliary processor unit interface, the data trace unit comprising electronic logic circuitry to electronically monitor in real-time parameters sufficient to define the load and store operations information that the core controller may assert, process information during events, select multiple address ranges for tracing, filter the information, and synchronize data trace information with instruction trace information. The load and store operations information comprises address, data, and byte enables of an operations indicator and a load/store indicator. The data trace unit includes: device control registers connected to the embedded core controller; event capture logic connected to the instruction side on-chip memory and the data side on-chip memory, having outputs to event filter logic, a FIFO array, and a FIFO control module; the event filter logic receiving store, load and address bus lines from the event capture logic, and returning a match signal to the event capture logic; the FIFO control module interfacing with the FIFO array, adapted to receive an event capture signal from the event capture logic, and output information to output control logic; the output control logic having an external interface to communicate via I/O pins, and a local bus interface to communicate to the embedded random access memory. Also included are software algorithms for reconstruction of data produced by the data trace unit with an instruction stream of data being executed.
In a second aspect, the present invention is directed to a data trace unit apparatus for a single chip integrated circuit embedded core controller designed to achieve a low bandwidth output path, comprising: a FIFO control and array for buffering the bursts of load and store events; a plurality of event filters to distinguish only those events in predetermined address ranges; an output path having a programmable width; a lost event indicator capable of accommodating an overrun of the FIFO; and, encoding circuitry for encoding an output control pinout, allowing for a variable number of output cycles per event.
In a third aspect, the present invention is directed to a real-time data tracing apparatus on an integrated circuit chip comprising: an embedded core controller that allows visibility of address and control signals being presented to caches; a data trace unit designed to acquire signals from the core controller through a data-side on-chip memory module interface and through an auxiliary processing unit interface, the data trace unit adapted to view the address and control signals being presented to the caches by the embedded core controller, capture store indicator, address, byte enables, and store data information from the on-chip memory module interface, and capture load data from the auxiliary processing unit interface; a processor local bus for interfacing the core controller with memory modules; a data trace port interfacing with the data trace unit; and, an instruction trace port connected to the core controller. The data trace unit comprises electronic logic circuitry designed to transmit information via the data trace port, the electronic logic circuitry adapted to adhere to procedural restrictions including: sending idle characters when no events are present; taking a snapshot of a current instruction address register from the core controller when an event is inserted into an empty FIFO array and transmission of an instruction address register is enabled; sending a control byte when there is a partial load/store or when not all byte enables are set; sending an appropriate number of address bytes as a function of an output control register setting; and, inserting a control character into an output stream at the point of losses when events have been lost since a previous event was transmitted, and resetting event counters. The data trace unit further comprises: a plurality of register sets connected to the device control register bus; event capture logic having electronic logic circuitry capable of capturing a load or store event data acquired from the on-chip memory and the auxiliary processor unit interface; a FIFO register control and a FIFO array having electronic logic circuitry for storing the event information; output control logic having electronic logic circuitry for transmitting information from the event off the integrated circuit chip; and, support logic to control data flow.
In a fourth aspect, the present invention is directed to a data trace unit apparatus for a single chip integrated circuit embedded core controller comprising electronic logic circuitry adapted to: access control, address, and data signal lines required to monitor the embedded core controller""s activities; perform data tracing independent of instruction tracing; synchronize with an instruction trace stream; allow for selection of multiple ranges for data tracing; report lost events to a FIFO array; and, output strobe signals to give a cycle accurate indication of when an event has been captured.